( / 6) mitsubishi 0107 M62352AGP 8bit 12ch d-a converter with buffer amplifiers 1 description m62352a is a cmos structured semiconductor integrated ciruict integrating 12 channels of built-in d-a converters with high performance buffer operational amplifierf or each channel output. 3-wire serial interface (di,clk,ld) method is used for the taransfer format of digital data to allow connection with microcomputer with minimum wiring do terminal is provided to allow cascading serial use. built-in buffer operational amplifiers are designed to operate or full-swing in the whole voltage range from vcc to gnd for each input/output. and their higher stability for capacitive load perfectly fits in to the use for electronic volume (vca) or the replacement for semi-variable resistor for tuning. features 12 bit serial data input (3 wire serial data transfer method, di, clk, ld) corresponds to ttl input for digital input (vinh 2v, vinl 0.8v) r-2r + segment method high performance 12 channel 8 bit d-a converters 12ch b uffer operational amplifiers opperating in the whole voltage range from vcc to gnd buffer operational amplifiers with high oscillation stability for capacitive load application adjustment or control of industrial or home-use electronic equipments such as vtr camera, vtr set, tv, and crt display. 10 11 12 13 14 15 16 17 18 19 2 3 4 5 6 7 8 9 di do ao12 ao11 vcc ld ao1 clk ao3 ao4 ao5 ao6 ao7 ao8 ao9 ao10 vdd ao2 20 gnd 1 vss pin configuration(top view) outline 20p2e-a d0 10 11 20 19 18 17 16 15 14 13 12 11 d-a l 8bit r-2r + segment d-a converter 8bit r-2r +segment d-a converter ch3 4 5 6 7 8 9 10 (12)
( / 6) mitsubishi 0107 M62352AGP 8bit 12ch d-a converter with buffer amplifiers 2 explanation of terminals symbol di serial data input terminal.12bit serial data is input to this terminal. clk serial clock input terminal.input signal from di terminal is input to 12bit shift register upon the rise of shift clock. 8bit d-a converter output terminal. built-in buffer amp.is connected to vcc. d-a converted voltage between vdd and vss is output to each terminal. power supply terminal. digital and analog common gnd function pin no. do serial data output terminal.serial data of 12bit shift register is output from this terminal. ld data is loaded to register when 'h' is input to ld terminal. ao1 ao2 ao3 ao4 ao5 ao6 v cc gnd v dd d-a converter high level reference voltage input terminal. ao7 ao8 17 18 11 9 14 16 15 19 2 3 4 5 6 7 8 12 13 ao9 ao10 ao11 ao12 20 10 block diagram for explanation of terminals 8bit latch 8bit d-a converter 8bit latch 8bit d-a converter 8bit latch 8bit d-a converter 8bit latch 8bit d-a converter (12) di v cc gnd v dd decoder ao1 ao3 ao10 ao2 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 12 bit shift register a5 a10 clk ld a1 a4 do 18 19 2 9 14 20 10 11 17 15 16 8bit latch 8bit d-a converter ao11 a11 12 8bit latch 8bit d-a converter ao12 a12 13 1 2 3 4 5 6 7 8 9 10 11 12 v ss 1 (8) v ss d-a converter low level reference voltage input terminal. 1
( / 6) mitsubishi 0107 M62352AGP 8bit 12ch d-a converter with buffer amplifiers 3 digital data format dac select data d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dac select data dac data msb lsb dac data 0 0 0 0 1 0 0 0 0 1 0 0 d4 d5 d6 d7 d0 d1 d2 d3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (vrefu - vrefl) / 256 x 1+vrefl[v] (vrefu - vrefl) / 256 x 2+vrefl[v] (vrefu - vrefl) / 256 x 3+vrefl[v] (vrefu-vrefl)/256 x 255+vrefl[v] vrefu[v] d-a output (256lsb) (255lsb) (3lsb) (2lsb) (1lsb) vrefu=v dd vrefl=v ss 1 : : : : : : : : : 1 0 0 0 0 1 0 (vrefu - vrefl) / 256 x 4+vrefl[v] (3lsb) first last 1 1 1 1 don't care 0 0 0 1 a1select 0 0 1 0 a2select 0 0 1 1 a3select 0 1 0 0 a4select 0 1 0 1 a5select 0 1 1 0 a6select 0 1 1 1 a7select 1 0 0 0 a8select 1 0 0 1 a9select 1 0 1 0 a10select 1 0 1 1 a11select 1 1 0 0 a12select 1 1 0 1 don't care 1 1 1 0 don't care d11 d10 d9 d8 dac selection 0 0 0 0 don't care ld clk si ao1~ ao12 d2 d1 d0 d8 d9 d10 d11 d7 d6 d5 d4 d3 timing chart (model)
( / 6) mitsubishi 0107 M62352AGP 8bit 12ch d-a converter with buffer amplifiers 4 absolute maxmum rating electric characteristics symbol topr tstg d-a converter high levelreference voltage power dissipation operating temperature storage temperature parameter conditions - 0.3 ~ 7.0 - 0.3 ~ 7.0 - 20 ~ 85 - 40 ~ 125 unit v v mw ratings supply voltage vcc pd 150 vout output voltage v v digital input voltage - 0.3 ~ v cc +0.3 in v - 0.3 ~ v cc +0.3 i refu reference voltage pin current 1.4 2 .5 v v ao i ao = 500a 0.1 -1.5 i ao ma differential nonlinearity nonlinearity -2.0 2.0 lsb lsb 0.2 d-a converter high level reference voltage range v dd (v refu ) buffer amplifier output drive range s dl s l szero s full co ro zero code error full scale error output capacitative load the output does not necessarily be the values within the reference voltage setting range.the output value is determined by the buffer amplifier output voltage range(vao). upper side saturation voltage=0.3v lower side saturation voltage=0.2v v refu = 4.79v without load (i ao =+0a) v refu =5v,v refl =0v,i ao =0a data condition: at maxmum current 3.5 v cc v cc -0.1 v cc -0.2 -1 -1.0 -2.0 5 1 1.0 1.5 2.0 0.1 ma v lsb lsb f ohm (vcc, vrefu=5v 10% , vcc vrefu, gnd, vrefl=0.0v, ta=-20 ~ + 85 c unless otherwise specified.) symbol supply voltage input leak current digital input low voltage parameter conditions v in =0 ~ v cc ratings min typ max unit v v v 4.5 5.0 5.5 a digital input high voltage v ol digital output low voltage i ol = 2.5ma v -10 10 0.4 vcc icc supply current clk=1mhz operation 3.5 0.8 2.0 ma v oh digital output high voltage i oh = - 400a v v cc -0.4 v cc =5 v, i ao =0a 1.5 v refl = 0.95v (15mv/lsb) v cc = 5.5v v ss (v refl ) gnd v cc - 3.5 d-a converter low level reference voltage range i ao = 100a c c symbol parameter conditions ratings min typ max unit buffer amplifier output drive range vdd vil iilk vih note: changes from m62352gp: digital input voltage corresponds to ttl spec. (vcc, vrefu=5v 10 % , vcc vrefu, gnd, vrefl=0.0v, ta=-20 ~ + 85 c unless otherwise specified.)
( / 6) mitsubishi 0107 M62352AGP 8bit 12ch d-a converter with buffer amplifiers 5 c l 100pf input output dut timing chart symbol clock "l" puise width data setup time data hold time parameter conditions ratings min typ max unit ld setup time 200 clock "h" pulse width clock rise time clock fall time d-a output settling time t ckl t ckh t cr t cf t dch t chl t ldd t chd the time until the output becomes the final value of 1/2 lsb 200 200 30 60 200 300 ns ns ns ns ns s ld "h" hold time t ldh 100 ns ns data output delay time t do c l 100pf ns 350 70 cl 100pf,vao:0.5 4.5v measurement circuit ld hold time t ldc 100 ns t ckl t cr t ckh t cf t dch t chd t ldh clk di ao1~ ao12 output do output t chl ld t do t chl t ldc t ldd t do (vcc, vrefu=5v 10% , vcc vrefu, gnd, vrefl=0.0v, ta=-20 ~ + 85 c unless otherwise specified.)
( / 6) mitsubishi 0107 M62352AGP 8bit 12ch d-a converter with buffer amplifiers 6 typical application do clk ld di vdd(vrefu) gnd vcc 11 10 20 15 16 17 18 ao4 3 ao3 2 ao2 19 ao1 18 mcu vss(vrefl) 1 4 ao5 ao8 7 ao7 6 ao6 5 ao11 12 ao10 9 ao9 8 ao12 13 note: m6235 2 agp has 3 terminals(vdd, vcc, and vss) to which constant voltage is to be applied. ripple voltage or spike noise to these terminals may worsen converting precision or cause erroneous operations. so be sure to use this device by putting cacpacitor between each terminal and gnd to get d-a conversion operation stabilized. output buffer amplifiers have high oscillation stability against capacitive load. this means that jitters by wirings around output terminals or capcitor between output and gnd(0.1uf max.) do not cause any problems with dac operations. connect capacitor(0.1uf or around) between output and gnd for protection from spark discharge when this device is used under such high electric field as that for instance of instruments with cathode ray tube.
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